everlight electronics co., ltd. http://www.ever light.com rev 2 page: 1 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu technical data sheet photolink- fiber optic receiver plr135/t6 features 1. high pd sensitivity optimized for red light 2. data : nrz signal 3. low power consumption for extended battery life 4. built-in threshold control for improved noise margin 5. good esd protection: up to 8kv 6. pb free 7. receiver sensitivity: up to ?27dbm (min. for 16mbps) up to ?21dbm (min. for 25mbps) 8. the product itself will remain within rohs compliant version. descriptions the optical receiver is packaged with custom optic data link interface, integrated on a proprietary cmos pdic process. the unit functions by converting optical signals into electric ones. the unit is operated at 2.4 ~ 5.5 v and the signal output interface is ttl compatible with high performance at low power consumption. applications 1. digital optical data-link 2. dolby ac-3 digital audio interface
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 2 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 package dimensions notes: 1. all dimensions are in millimeters. pin function: 1.vout 4.nc 2. general tolerance : 0.3mm 2.gnd 5.nc 3.vcc pcb layout for electrical circuit notice: 1. unit:mm 2. pcb tolerance:1.6m m
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 3 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 absolute maximum ratings( ta = 25 oc) parameter symbol rating unit supply voltage vcc -0.5 ~ +5.5 v output voltage vout vcc +0.3 v storage temperature tstg -40 to 85 oc operating temperature topr -20 to 70 oc soldering temperature tsol 260* oc * soldering time 10 s. electro-optical characteristics(ta=-20~70 ,vcc=3v) parameter symbol conditions min. typ. max. unit power supply voltage vcc - 2.40 3.00 5.50 v peak sensitivity wavelength p - - 650 - nm maximum receiver power pc,max refer to fig.1 - - -14 dbm minimum receiver power pc,min refer to fig.1 -27 - - dbm dissipation current icc refer to fig.2 - 4 12 ma high level output voltage v oh refer to fig.3 2.1 2.5 - v low level output voltage v ol refer to fig.3 - 0.2 0.4 v rise time t r refer to fig.3 10 20 ns fall time t f refer to fig.3 10 20 ns propagation delay low to high t plh refer to fig.3 - - 120 ns propagation delay high to low t phl refer to fig.3 - - 120 ns pulse width distortion ? tw refer to fig.3 -25 - +25 ns refer to fig.3, pc=-14dbm - 1 15 ns jitter ? tj refer to fig.3, pc=-27dbm - 5 20 ns transfer rate t nrz signal 0.1 - 16 mb/s
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 4 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 measuring method *fig.1 measuring method of maximum and mini mum input power that receiver unit need transmitter standard plastic optic fiber cable plr135 receiver unit control circuit optical power meter *fig.2 measuring method of dissipation current vin standard transmitter unit signal input 47uh 16 mbps nrz "0101" successive signal input vcc gnd standard plastic optic fiber cable plr135 receiver unit 3v a gnd 0.1uf vcc vout
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 5 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu l2:47uh c1:0.1uf vout 5v l2 vcc gnd c1 receiver unit c2 c2:30pf (suggestion) plr135/t6 *fig.3 measuring method of output voltage, pulse and jitter output vin 16 mbps nrz "0101" successive signal input standard transmitter unit input signal input t w = t phl -t plh tj2 tj1 50% 50% ch2 47uh t t plh phl vcc gnd ch1 standard plastic optic fiber cable plr135 receiver unit 3v a gnd 0.1uf vcc vout application circuit (1) general application circuit for vcc=3v (2) general application circuit for vcc=5v l2:47uh c1:0.1uf vout 3v l2 vcc gnd c1 receiver unit note: for having good coupling, the c1,c2 capacitor must be placed within 7mm
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 6 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 typical electro-optical characteristics curves *fig.4 power supply voltage vs. minimum receiver power *fig.5 transfer rate vs. minimum receiver power 2.02.53.03.54.04.55.05.56.0 -20 -22 -24 -26 -28 -30 operating transfer rate 16mbps 25mbps optical input sensitivity (dbm) operating voltage (v) 0 5 10 15 20 25 -18 -20 -22 -24 -26 -28 -30 -32 operating voltage vcc=3.3v optical input sensitivity (dbm) transfer rate (mbps) note: before using the plr135 device, please confirm the minimum sensitivity at different operating voltage and transmission rate.
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 7 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 reliability test items test sample size number (n) no. item test condition hour/cycle (piece) failure (c) 1 soldering heat 260 oc 5 oc 10 seconds 22 n=22, c=0 2 high temp. storage ta=100 oc 1000hrs 22 n=22, c=0 3 low temp. storage ta=-55 oc 1000hrs 22 n=22, c=0 high temp. & 4 humid. test ta=85 oc , rh=85% 1000hrs 22 n=22, c=0 -55 oc ~~~~ 85 oc 5 temperature cycle (30min) (5min) (30min) 300cycle 22 n=22, c=0 -10 oc ~~~~ 100 oc 6 thermal shock (5min) (10sec) (5min) 300cycle 22 n=22, c=0 7 dc operating life vcc=3v, ta=25 oc 1000hrs 22 n=22, c=0
everlight electronics co., ltd. http://www.ever light.com rev 2 page: 8 of 8 device no.: dpl-135-011 prepared date:07-25-2005 prepared by: chin-chia hsu plr135/t6 application notes: plr135 series pc b layout for motherboard integration to achieve better jitter and low input optical power performances, several pcb layout guidelines must be followed. these guidelines en sure the most reliable plr135 pof performance for the motherboard integration. failed to implement these pcb guidelines may affect the plr135 jitter and low input power performances. 1. careful decoupling of the power supplies is very important. place a 0.1uf surface mount (size 805 or smaller) capacitor as close as (less than 2cm) to the pof vdd and gnd leads. the 0.1uf act as a low impedance path to ground for any stray high frequency transient noises. 2. to reduce the digital noises form the digital ic on the motherboard, the planar capacitance formed by an isolated vcc and gnd planes is cr itical. the pof device must be mounted directly on these two planes to reduce the lead parasitic inductance. 3. the isolated vdd and gnd planes must be conn ected to the main vcc and gnd (digital) planes at a single point using ferrite beads. the beads are used to block the high frequency noises from the digital planes while still allowing the dc connections between the planes everlight electronics co., ltd. tel: 886-2-2267-2000, 2267-9936 office: no 25, lane 76, sec 3, chung yang rd, fax: 886-2267-6244, 2267-6189, 2267-6306 tucheng, taipei 236, taiwan, r.o.c http://www.everlight.com
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